• Develop and simulate an algorithm for execution using DNA computing
  
  
• Develop and simulate an algorithm for execution using quantum computing

• Mapping applications to nanoarchitectures

Pick an important algorithm and map it to a nanoarchitecture (e.g., FFT on PIP, MPEG on array-based arch, etc.). You must develop a behavioral simulator of the nanoarchitecture and implement the algorithm to obtain performance estimates of the algorithm. A comparison to today’s or future CMOS processor performance is required and can be obtained by using simplescalar.

• Compute effective density.

Perform an analysis of defect rates versus functionality versus density. Examine various aspects from raw devices through sophisticated circuits with complex interconnect.

• SPICE simulation of nano devices and circuits

Pick a nanodevice (e.g., RTD, Silicon nanowire FET, any device that you can find a well behaved IV curve for), then develop spice simulation models to obtain performance and power estimates. This should be complemented by comparisons to 180nm, 75nm, and 45nm CMOS implementations (we will provide these spice models).

• Compiling for NANA or SOSA

NANA and SOSA are two distinct architectures that we’ve developed here at Duke. The goal of this project is start developing compiler support for this architecture. To this end, this project will take an existing compiler infrastructure (e.g., the itanium compiler) and modify it to output appropriate instruction sequences for the NANA architecture. Expectations for this project are to achieve compilation of simple code segments (e.g., sequential code and simple loops).

• Hybrid Architectures

What structures in current CMOS would you replace with nanoscale components. You’re free to choose any type of nanotechnology (devices + circuit techniques)

• Architectural implications of converging dynamic and static power consumption.

A nice feature of CMOS circuits is that most power is typically consumed when transistors switch state. This dynamic power consumption can be reduced by turning off portions of the chip (not allowing them to switch) when they are not in use. However, as feature sizes continue to decrease, the amount of leakage current increases, thus power consumed when the transistor is not switching, increases. What is the trend in the difference between dynamic and static power as feature sizes decrease. Do they become so close that it is no longer worth trying to reduce dynamic power?

• Nanocell related projects

1. Design and simulate architectural structures built using the connected nanocell circuit techniques (e.g., various finite state machines, data path, register file, caches)

2. DRAM + Nanocell

Design and simulate nanocell-based circuits that use a DRAM cell as the signal restorative component rather than NDR bistable latches.

3. Asynchronous Nanocells

Eliminate the need for clock distribution networks in nanocell circuits by using asynchronous designs.

4. Nanodentrite stearing

It is possible to “grow” a wire by having nanoparticles align when applying a voltage. Explore techniques to use these grown wires to extend the macroscale input and output pins of a nanocell to obtain better signaling.

• Fabrication facility cost analysis

Research the cost of silicon fabrication facilities and compare this to the cost of fabrication facilities required for chemical self-assembly (this is probably something similar to a chemical plant).

• Market trends vs. technology parameters

Explore various market trends (e.g., market capitalization, volume, etc.) versus one or more technology parameters (e.g., feature size, power, etc.)