DUKE UNIVERSITY
Department of Electrical and Computer Engineering
ECE 52 Assignment 10

Due by midnight. (Use the Bb site, late assignments will be penalized 25%)

1) Design and test the components of the protocomputer:

Unlike in class, make the data width 12 bits and the address width 8 bits. This will fit on the UP1 boards in lab (if you want a REAL test) and the memory file isn't too, too big.

Complete the logic (structural VHDL only, LPMs are OK) of the protocomputer, including all 12 instructions in its instruction set architecture, using the format developed in class.  Use Quartus to design each component, including the ALU and demonstrate that each works (independently).

Pay attention to the final destination of the enable signals; for instance, since
MAR_IN_ENABLE is turned on by multiple AND gates, you will need an OR gate to collect these possible sources together and trigger the actual signal.

Simulate and provide timing waveforms (save as JPGs, use screen capture [the "Print Screen" button] and MSPAINT) for the: MAR, MBR, ALU, AC, SP, IR, PC, and STATUS components.
You do not need to exhaustively test each component, simply demonstrate all necessary functionality. E.g., the SP must increment, decrement, assert a bus value, and read a bus value, etc.

2) Simulate the protocomputer:

Once the pieces are working, integrate them to form the protocomputer. Verify that your fetch and execute cycles work correctly. Your main memory is supplied with initial values defined in main_memory.mif (which you can edit in Quartus- this is where you put your program). The value in the first position (0) should be the first value to be loaded into the IR when the machine is reset.

If all is good and after you have tested each instruction, simulate the absolute value program below:

Location	OPCODE	ADDRESS
00	READ	0C
01	WRITE	0D
02	AND	0E
03	JNZ	05
04	HALT	00
05	READ	0C
06	NEG	00
07	ADD	0F
08	WRITE	0D
09	HALT	00
0A	UNUSED
0B	UNUSED
0C	input value
0D	RESERVED
0E	800
0F	001

(you will need to enter this into your main_memory.mif)

Provide an output waveform (JPG) of the execution that is formatted like the one below: (you can ignore/delete the FLEXSWITCHES and SEG1, SEG2 outputs unless you plan to program one of the lab FPGA boards.)




3) Programming your computer:

    a) Modify the Absolute Value example program to operate as a subroutine called ABS which takes one
integer argument in the AC and returns the absolute value of that number in the AC.

   b) Create a second subroutine called DOUBLE that takes one integer argument in the AC and returns twice
that value in the AC.

   c) Have your main program (beginning at instruction 0 in memory) retrieve a number from
memory location 0x0C, call ABS and DOUBLE, and store the result in memory location 0x0D, so that
MEM(0x0D) = DOUBLE(ABS(MEM(0x0C))

  d) Simulte the program execution and provide an output waveform.



****************** IMPORTANT NOTES *********************

Compress your entire protocomputer project directory (include your reasonably named waveform JPGs in this directory, too) and submit this ONE file called YOURNAME.ZIP to the Blackboard site.

GRADING CHECKLIST:
1. Waveforms for all component tests.
2. Waveform for the execution of the absolute value program.
3. Waveform for the execution of your modified double(abs(...)) program.
4. Your structural VHDL code and project files (we will run an unspecified test program on your computer.)
5. Documentation: Include your OPCODE definitions (e.g., which code did you use for HALT?)