DUKE UNIVERSITY
Department of Electrical and Computer Engineering
ECE 52 Assignment 7
Due in class
Please do problem 5.13 - since the answer is given in the book, be sure
to show how you got your answer!
Compare this with the number of gates needed to build an 8-bit
ripple-carry adder with the same fan-in
constraint.
Please also do problem 5.18
Also, please do this:
Design and simulate a two input (L and M) clocked latch (level
sensetive) with three outputs (Q, R, and S) that behave as follows:
(use any variety of VHDL and a timing simulation, print out waveforms
and source VHDL)
L M | Q(t+1) | R(t+1) | S(t+1)
------------------------------
0 0 | S(t) | Q(t) | R(t)
0 1 | 0 | 1 | 1
1 0 | 1 | 0 | 1
1 1 | Q(t) | R(t) | S(t)
Please also do these problems: 6.1, 6.4, 6.7, 6.11, and 6.16.
(5.13 and extra - 10 points; 5.18 is 5 points; latch is 10 points, other problems are 5 points each)