|
Date
|
Lab
|
Lectures
|
Readings
|
Assignments Due
|
|
1/11
|
No Lab
|
1. (PDF)
Introduction,
switching-networks, AND/OR/NOT
|
Preface, Chapter 1,
begin
Chapter 2
|
|
|
1/16 |
Lab
0
|
2. (PDF)
Boolean
algebra,
synthesis, NAND/NOR, full adder
|
Finish Chapter 2
|
|
|
1/18
|
3. (PDF)
Combinational
circuits, XOR/XNOR, logic synthesis, CAD
|
Ch.
3 (pp. 73-93)
|
Assignment
1 due
All assignments (throughout
the semester) are due at lecture
I.E., if
it's LATE that means NO_CREDIT (i.e., 0%)
|
|
1/23
|
Lab
1 |
4. (PDF)
Continue synthesis and CAD, basic
VHDL
|
Ch.
3 (pp. 94-113)
|
|
|
1/25
|
5. (PDF)
Review MOSFETs,
NMOS/PMOS, CMOS, PLDs, PALs, CPLDs,
comparators
|
Ch.
3 (pp. 114-134)
|
Assignment
2 due
|
|
1/30
|
Sample Quartus project file
(w/
pre-lab)
Lab
2
FPGA/CPLD
programming
tutorial
|
6.
(PDF)
FPGAs,
fan-in / fan-out, buffers, transmission
gates, tri-state gates
|
Ch.
3 (pp. 134-145)
|
|
|
2/1
|
7.
(PDF)
K-maps: SOP, POS, X; function
minimization
|
Ch.
4 (pp. 164-202)
|
Assignment
3 due
|
|
2/6
|
8.
(PDF)
Optimization
algorithms, multiple
outputs
|
Ch.
4 (pp. 203-228)
|
|
|
2/8
|
9. (PDF)
Factoring, Quine-McCluskey, more VHDL
|
Ch.
5 (pp. 246-256)
|
Assignment
4 due
|
|
2/13
|
Lab
3
|
10. (PDF) Number
systems, bin/ octal/
hex
|
Ch.
5 (pp. 256-278)
|
|
|
2/15
|
11. (PDF) Sign
magnitude, 1's &
2's complement, negative numbers
|
Ch.
5 (pp. 278-309)
|
Assignment
5 due
|
|
2/20
|
Lab
catch-up week
|
Midterm
I
No notes, no calculators, no book,
1 page of exam notes (8.5"x11")
|
|
2/22
|
Midterm I post-mortem, begin lecture 12.
|
|
2/27
|
(w/
pre-lab)
Lab
4
|
12.
(PDF)
9/10's complement, memory, and latches
|
Ch.
6 (pp. 316-339)
|
|
|
2/29
|
13.
(PDF)
More latches, flip-flops, MUX logic (again)
|
Ch.
6 (pp. 339-363)
|
Assignment
6 due
|
|
3/5
|
Lab
5 |
14.
(PDF)
Parity, fast
adders, fixed-point,
floating point, ranges, ASCII, intro to FSMs
|
|
|
|
3/7
|
15. (PDF)
Counters, finite
state machines
|
Ch.
7 (pp. 380-398)
|
Assignment
7 due
|
|
3/12
|
No Lab |
No Class |
3/14 |
No Class |
|
|
|
3/19
|
Lab 6
|
16.
(PDF)
Registers,
counters, more FSMs,
state minimization,
FSM analysis, more VHDL
|
Finish
Ch. 7
|
|
|
3/21
|
17.
(PDF)
More FSMs, comb. wrap-up, memories. |
Ch.
8
|
Assignment
8 due |
|
3/26
|
(Continue
Lab 6 if needed)
Lab
7
Project
Proposals due in lab
|
18.
(PDF)
More FSMs,
protocomputer
introduction, RTL ALU,
control
design
|
|
|
|
3/28
|
19.
(PDF)
Protocomputer continued...
|
|
Assignment
9 due
|
|
4/2
|
Continue
Lab 7
|
Midterm
II
No notes, no calculators, no book, 2 pages
of exam notes (8.5"x11")
|
|
4/4
|
20.
(PDF) More
protocomputer parts, optimizations, JSR/RET, compilers
|
|
|
|
|
4/9
|
Project
simulations
due this week
|
21.
(PDF) Turing
machines,
asynchronous design, hazard avoidance,
flow
tables,
stable
states, races
|
|
|
|
4/11
|
22. (PDF) Asynchronous
design examples
|
|
|
|
4/16
|
Continue
Lab 7 |
23. (PDF)
Midterm II post-mortem
Encodings:
Gray,
Reed-Solomon, RAIDs, parity,
Hamming, error
correcting
codes
|
|
|
|
4/18
|
24. (PDF) Testing
logic
circuits
|
Ch.
9
|
|
|
4/23
|
Project
demos |
25.
(PDF) Path
analysis, built-in-self-test, signature generation.
|
|
Assignment
10 due
(Reference and
example
parts)
Protocomputer VHDL template and a sample main_memory.mif file
(start with this, defer to its
specifications) |
|
The
registrar says:
ECE 52L Final Exam: Tuesday, April
29, 2:00PM - 5:00PM.
|
