DUKE UNIVERSITY
Department of Electrical and Computer Engineering
ECE 52 Lab 2

  • Lab report due date: The date you start your next lab exercise (i.e., lab 3)
  • IMPORTANT: Complete Parts A and B (the Quartus pieces) before your first lab session! This lab will take two (2) weeks.
Lab Objectives Design of Two-Bit Magnitude Comparator:

   All simulations should be complete prior to the FIRST lab session so you can devote your time to getting the hardware working.  If at least one member of your group has a laptop with Quartus installed, it might be useful to bring it to lab so you don't have to worry about sftp'ing your work around from machine to machine.  If you need to, however, you can upload your designs from your own PC to your OIT or ECE accounts, and then sftp them to the lab PCs from there.  There is an option to archive an entire project as a single file; that is the easiest way to ship a complete design around.

   The objective of this lab exercise is to introduce the student to the usage of complex logic modules, such as multiplexers, in the implementation of other more complex logic units. The multiplexer chip available in the lab is the 74LS151 TTL component. Its functional description is on the course website. Study its function and input/output connections carefully  before you make actual use of the chip.

   The complex logic unit we wish to implement using this multiplexer is a Two-Bit Magnitude Comparator module. This module is intended for configuring, eventually, an 8-Bit comparator using four copies of the Two-Bit Magnitude Comparator module.
Part-A
 Hardware Implementation

      The Two-Bit Magnitude Comparator module will be implemented using the 74LS151 TTL component and "glue" logic (ANDs, ORs,...) sparingly. The input and output to the module are depicted in Fig._1.   Indicate the values of your output signals EQ(i) and GT(i) with LEDs on your protoboards (properly driven by a 74LS244 buffer or similar chip). The inputs will come from the DIP switches; note the pulldown resistor on the DIP switch should be about 1K; there are problems using the prior default 22K resistors with this lab!
                         
                            (Local Inputs)  
                       A(k+1) A(k)    B(k+1) B(k)
                       |      |       |      |   
                       |      |       |      |  
                       |      |       |      | 
                     ===========================
                     :         Two-Bit         : 
      EQ(i+1) ------>:                         :------->EQ(i)  
                     :       COMPARATOR        : 
      GT(i+1) ------>:                         :------->GT(i)   
                     :       i_th MODULE       :  
    (Input from      =========================== (Output of i_th  
     prior module)                                module) 
                               Fig. 1
   
      The comparison is carried out from left-to-right on the operands:

         A = A(n-1)A(n-2)...A(k+1)A(k)...A(1)A(0)

         B = B(n-1)B(n-2)...B(k+1)B(k)...B(1)B(0) 

      In order to carry out the comparison, one must cascade as many modules of the type depicted in Fig. 1 as needed to accommodate the  n-bit  operands.

      Obtain the design equations for the Two-Bit COMPARATOR module. Express the equations in a way that leads to a hardware implementation which utilizes multiplexers and "glue" logic gates, sparingly! That is, use as few multiplexers and logic gates as possible. 
Part-B
 Simulation   

      A simulated version of the Two-Bit COMPARATOR module is required.

      Use Quartus to design and simulate the module. The 74151 component (and essentially all other 7400-series parts) are
      prebuilt in Quartus - you are encouraged to use the predefined 74151 module in your simulation.  It is available under SYMBOL->OTHERS->MaxPlus2 in the schematic editor.  For your glue logic, please use primitive "AND", "OR" and "NOT" gates from SYMBOL->PRIMITIVES->LOGIC.

      Label all the terminals of the module clearly and properly so that it can be conveniently cascaded to configure comparators of larger sizes (i.e., 8-bit, 16-bit, etc.).
Part-C
 Design and Simulation of an 8-bit Comparator

      Using the Two-bit Comparator module that you have created, configure and simulate an 8-bit Comparator using Quartus.  If you have done your design modularly, this should be trivial!

      In the lab, when your own 2-bit comparator is working, cascade yours with the comparators from three other groups (or as many other groups as is possible) to demonstrate a hardware 8-bit comparator.
Week 2This part of the lab (week 2) is designed to introduce you to using programmable logic chips.  You should be able to complete it during the designated laboratory session.
Part-DCPLD programming:

   1. Take your 8-bit magnitude comparator from Part C (4 cascaded 2-bit comparators), as simulated in Quartus, and compile the design for the Altera MAX 7000 CPLD.

   2. Determine where your I/O pins are, and wire up the on-board switches and LEDs appropriately.

   3. Download, and test your design.
Part-EFPGA programming:

   1. Take the same design, MODIFY IT TO BE A 4-bit COMPARATOR and recompile it for the Altera FLEX 10K FPGA.  Assign the I/O pins appropriately;

   2. Download and test your design. (Use only 4 bits since the FPGA side only has 8 switches total)
Lab Report Your Lab report should include the following items:
      1) Title page: Your name; Title of the experiment; Date
      2) The lab handout
      3) The design equations for EQ(k) and GT(k) 
      4) Results of your simulations for the Two-bit and 8-bit Comparators. Provide all schematics and waveform traces generated by Quartus or Max-plusII, clearly labeled.
      5) Provide the logic circuit diagram used in the hardware realization of the Two-bit Comparator module, and the printed record from the HP Logic Analyzer used to observe and verify the logical behavior of the module. Label all traces clearly. 
      6) Comment on the advantages and disadvantages of "modular" vs "monolithic" design in general, and in particular when applied to the 8-bit Comparator of this experiment.
      7) Comment on any changes you needed to make to your original design for the CPLD and FPGA implementation; report on the results of testing the CPLD and FPGA versions.
      8) Concluding observations and comments.