|
|
| Lab Objectives | VHDL
BCD Adder: This is a one week lab. Since we will not be building any hardware per se you should be able to finish anything you don't complete during the session on your own. This week we will use VHDL to design a BCD full adder cell, and couple several of these cells together to add multiple digit decimal numbers. (Note a typo on page 298 of some printings of our textbook: near the top of the page, the correct statement should be if Z>9 S=Z+6 and carry-out = 1 , not X=Z+6 as in some printings.) An important note about your textbook: "There appears to be an unclarity in Brown & Vranesic's pg. 301 schematic of a BCD one-digit adder. If you'll notice, the 4-bit adder accepts its inputs as the four bits of one addend on the left, and the four bits of the other addend on the right. Below that, there is a 2-bit adder that does not explicitly specify what its inputs signify. A logical individual might assume that the inputs signify [x1,x0,y1,y0] (i.e. the first two-bit addend, followed by the second two-bit addend). However, this does not appear to be the case; the order of the inputs, by my inspection, is [x1,y1,x0,y0]. In other words, the addends to the 2-bit adder are interleaved. Take heed; otherwise, your adder will unconvincingly declare the sum 4+0 to be 2!" |
| Part-A |
Design a VHDL package (refer to
page 283 in your text) to implement a one-digit BCD adder cell using
STD_LOGIC data types in the structural style.
You may use vectors if you wish but please do not use the built-in
arithmetic operations available for STD_LOGIC_ARITH and related types,
and do not use a conditional
assignment (i.e., the WHEN statement in 5.37). You are free to use
the
circuit given in the chapter as inspiration for your structural code. |
| Part-B |
Call two instances of your
BCDadd component from another file to create a 2-digit BCD adder. |
| Part-C | Create a BCD-to-seven segment subcircuit using either structural or behavioral VHDL; wire two instances of this circuit to the two output digits of your BCD adder. |
| Part-D |
Target the FLEX FPGA available
on our lab boards and simulate your design; determine how long it takes
your circuit to add 2 2-digit BCD numbers. Be sure your test case
involves a worst-case ripple carry. |
| Part-E | Wire the Altera boards so that two of your digits are input via the "FPGA" dip switches; the other two input digits need to be jumpered from one bank of the "MAX" dip switches. Use the two 7-segment LEDS on the FLEX side, plus one discrete LED for overflow out of the most significant digit so that we can view the output of your circuit. Download and go! |
| Part-F |
Reimplement the BCD full adder
cell using the full power of the built-in VHDL integer operations (i.e.
figure 5.37!), again call 4 instances of the component to build a 4
digit BCD adder and target our FPGA chip. **Note you will have to modify the code in 5.37 to account for carry in and carry out functionality.** Time the resulting circuit and compare it with your manual design. Peruse the compiler output files to compare the number of logic blocks used by your manual design and the automated design. (Which design was more compact? Which was quicker for you to develop?) It should be clear that what we have built would be a good foundation for building a 4-function calculator circuit! |
| Lab Report | Document the schematics and
simulation results for each part. |