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| Lab Objectives |
The objective of this lab exercise is to introduce the student to
memory elements used in the design of sequential circuits, and to make
use of such elements in the actual implementation of a sequential
machine of the pulse input type. This is intended to be a
1-week lab. |
| Part A |
The 74LS00, 74LS10, and 74LS20
are 2, 3, and 4 input NAND gates respectively. Hook these up in the
oscillatory feedback configuration (i.e. n-1 inputs tied to Vcc, and
the output routed to the n-th input) and measure the frequency of
oscillation in each case. Note! Be sure to remove power from the other two chips while measuring each chip. These measurements may be tricky to get a lock on; be sure to use the 150 MHz oscilloscopes in the lab (some are 100 MHz). After you have measurements from each chip separately, observe one output (say the 4-input chip) and reconnect power to the 2-input chip. What is going on? After you have puzzled over this a bit, observe measurements of the 2-input gate on a wire-wrapped board that is available in the lab. Discuss the implications of what you have observed. |
| Part B | Construct an S-R latch from two cross-coupled NOR gates (74LS02) and characterize its behavior with the oscilloscope. Verify all state transitions; be sure to characterize what happens in the S-R both set state. Give a complete description of the experimental set up and of your measurement/observation methodology. |
| Part C |
The TTL
chip 74LS109 implements a JK_FF, and it is available in the laboratory. Experiment with it by verifying its functional behavior. Reproduce the entire state-transition table for the JK_FF and characterize as in Part-B. |
| Part D |
Convert the 74LS109 to D_FF functionality by
adding appropriate combinational logic. Verify the behavior of your
circuit as in Parts B and C. |
| Part E | Protocomputer Preparation : Design
and simulate a 16 bit wide 2:1 MUX which selects between the output of
16 X 2-bit wide AND gates and 16 X 2-bit wide OR gates. The OR and
AND gates
should use the same two 16 bit inputs (e.g., Zor(i) = X(i) + Y(i),
Zand(i) = X(i) * Y(i)) Build your design using only structural VHDL and demonstrate its funtionality to your TA for a random pair of inputs using the MUX to alternate between the two functions. HINT: investigate the VHDL "generate" keyword. |
| Lab Report | Your Lab report should include
the following items: 1) The results of your measurements from Parts A, B, C, and D. 2) Commentary on the results. 3) Document your results from Part E. (Include timing simulation results!) |