DUKE UNIVERSITY
Department of Electrical and Computer Engineering
ECE 52 Lab 7 - Final Project

  • Lab report due date: Sign-up for a demo slot. No changes to this schedule will be permitted after the first demo begins and missing your demo slot will yield a letter grade reduction. The write-up is due by the end of the final demo period. TURN IN AN ELECTRONIC COPY OF YOUR REPORT THROUGH BlackBoard (Use the Digital Dropbox- Put your group member names in the comment field)!
  • IMPORTANT NOTE ABOUT REPORT FILE FORMAT: RTF or PDF, ONLY! NO Word 2007 files! (MS Word can save to RTF)
  • You will have 5min to demo your project at a lab station- thus, 2 benchs will be unavailable for use on demo-day... so, complete your project in advance of demo-day!
  • Students from the lab on which demo-day lands will have priority at all remaining benches. (even so, you are also encouraged to complete your project in advance of demo-day!)

Pre-LabPrepare a project proposal:

  1. Include a preliminary problem statement (see lab objective below) and a design sketch.
Your design can be high level and block oriented. For example, if you need a register file simply draw it as a monolithic block to be filled in later. You do not need design equations, minimal logic, or VHDL at this point.

  2. Estimate the resource requirements for your design (i.e., gate count per block.)
Build your estimates from small peices (NAND gates to multiplexers, etc.)
Your estimate will necessarily be a rough guess since you don't have a complete design yet. However, now is the right time to understand the limitations of the FPGA/CPLD and determine what resources you will need (within a factor of 2 or so...)
Lab Objectives
For our final lab experience, we will design and implement substantial digital systems. Below are a number of possible systems you can work with, or you may propose your own.  We will implement these systems on our FPGA boards in either structural VHDL (except for next state transitions) or schematic capture.

Most projects will probably require adding additional input and/or output devices to the FPGA via an external protoboard (i.e. additional LEDs or switches.) These projects will test your ability to implement combinational and sequential logic, as well as your ability to express a real-world problem in the precise terms needed to reduce it to a state machine.

We will use the remaining lab sessions to work on these projects, and we will also arrange extra time when the lab is open to you in afternoons, evenings, and/or the weekend. Your TAs will let you know the after-hours times those weeks.

IMPORTANT GRADING INFORMATION: Your design must first pass a simulation test (conducted by your TA) before beginning to prototype your hardware- this will include a verification that your design uses only structural VHDL, except in next state transitions, or schematics and that it is functional. Failure to pass the simulation test by the end of the semester will result in a 50% reduction in your score. Failing to complete your hardware prototype by the end of the semester will result in a 25% reduction in your score.

BY FAR THE MOST IMPORTANT ASPECT OF THE PROJECT IS TO DEMONSTRATE A FUNCTIONAL DESIGN.

Each project listed below (and any custom project) must be designed to cover:

  1. Human-machine interfaces (i.e., human readable displays, user-friendly knobs, etc.)
  2. Memory
  3. A selection process (i.e., configuration, product selection, game input, etc.)
  4. State updates (i.e., a significant finite state machine)
  5. Mathematics (i.e., a computation is performed during operation)

Possible projects (choose one):

1) Vending machine:  design the control for a real vending machine - a minimal set of assumptions would be that the machine accepts all common coins, has items with at least 4 distinct prices (or more generally a looked up price per item in multiples of 5 cents), makes change intelligently (i.e. issues minimal number of coins in change and is smart enough to give 2 nickels when the machine is out of dimes), senses when a selected item is empty, and has a "coin return" switch to abort a transaction. A timeout between coin insertion and selection should also return any coins. Display the total amount the user has inserted (7-segment displays) and generate a "Vend-productA", "Vend-productB", ..., "Sold-out", "More cash", "Return nickel", "Return dime",..., output signals (can be LEDs). You must also provide a mechanism to restock the machine with both products and coins (for change). An internal display must also track statistics about product selections and revenues (you may use a toggle switch to share the 7-segment displays).

2) Traffic light controller: design the control for the traffic lights at a major intersection (4 roads, 4 turn lanes), including: sensors in lanes to trigger cycle changes, timeouts to guarantee certain minimum and maximum cycle times regardless of traffic, smart left turn lanes (only active if a car is waiting to turn left). Terminate a cycle early when no traffic has been detected for an appropriate interval. Include the pedestrian crosswalk buttons and an emergency vehicle override (turn lights green when emergency vehicle is approaching). Include a display indicating how much time is left in the current cycle and a running average of some (any!) measure of traffic in each direction (e.g., number of cars per second).

3) Programmable combination lock:  We used a simple sequence recognizer as our first finite state machine example. Consider a more sophisticated combination lock with provision for entering a user-specified code (decimal or alphanumeric), a timeout-reset if no button is pressed for a given interval, and a permanent lockout if an incorrect code is entered more than k times in a given interval.  A supervisory override code that generates an extra output signal and resets the code should also be added. Use a 7-segment display to indicate the status of the lock, e.g. "L" for locked, "U" for unlocked, "H" for lockout, etc. If the user does not enter a new code, the code should be permuted by a simple algorithm (such as "add 1 to each digit") each time it is used.

4) Encrypted communications controller: Design a system that sends encrypted words of data back-and-forth between two users over NO MORE than 4 wires (think "parallel to serial conversion). The data can be encrypted using any method you prefer- and therefore, the plain bit pattern should never appear on the communication lines between the users. Besides encryption, your design must deal with a number of asynchronous activities like "RESET" (resynchronize both ends) and "RECODE" where a user (on either end) may request the encryption scheme be recoded with a new key (you must accept a new key as input on each side). Your interface must also display pre- and post- encrypted values on both sides. Also, identify possible security vulnerabilities in your design and hypothesize ways to fix them.

5) Custom (Please arrange for a meeting with me OR your TA before the design proposals are due to define the project requirements.) If we have not met to discuss your custom project then a custom project proposal will not be accepted.

Lab Report Your report should:

1) describe the real-world problem you are solving

2) show how this problem is precisely and concisely stated as a digital design
   problem (i.e. truth tables, state diagrams)

3) discuss your implementation decisions in implementing your design (i.e. why
   a certain kind of flip-flop or latch, why Mealy or Moore, etc.).

4) describe and document your VHDL implementation of the project

5) demonstrate the correct operation of the circuit by appropriate capture of
   simulation and actual logic analyzer traces where possible.

6) document the precise contributions (design contributions) of each member of the group to the project.
A blanket statement "We worked equally on all parts" will not suffice!