Pratt School of Engineering
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EDUCATION
  • PhD, University of Wisconsin - Madison, 2002
  • MS, University of Wisconsin - Madison, 1998
  • BS, Duke University, 1996

Daniel J Sorin
  • Office Location: 209C Hudson Hall
  • Office Phone: (919) 660-5439
  • Email Address: sorin@ee.duke.edu

    • Dr. Daniel Sorin is an associate professor of Electrical and Computer Engineering and of Computer Science. His research interests are primarily in computer architecture and dependability.

    Specialties
    • Computer Engineering
      Computer Architecture
      Fault Tolerance
      Reliability

    Research Areas

      The primary focus of my research is to improve the dependability of computer architectures. My research group is developing novel, low-cost mechanisms for comprehensive error detection, fault diagnosis, and reconfiguration in response to faults.

    Recent Publications More Publications

    1. Meixner, A. and Sorin, D.J., Dynamic verification of memory consistency in cache-coherent multithreaded computer architectures, 2006 International Conference on Dependable Systems and Networks, (2006), ppt. 10 pp. - [abs]
    2. Bower, F.A. and Sorin, D.J. and Ozev, S., A mechanism for online diagnosis of hard faults in microprocessors, Proceedings. 38th Annual IEEE/ACM International Symposium on Microarchitecture, (2006), ppt. 12 pp. - [abs]
    3. Meixner, A. and Sorin, D.J., Dynamic verification of sequential consistency, Proceedings. 32nd International Symposium on Computer Architecture, (2005), ppt. 482 - 93 [abs]
    4. Dwyer, C. and Lebeck, A.R. and Sorin, D.J., Self-assembled architectures and the temporal aspects of computing, Computer (USA), vol. 38 no. 1 (2005), ppt. 56 - 64 , [34] [abs]
    5. Li, T. and Lebeck, A.R. and Sorin, D.J., Spin detection hardware for improved management of multithreaded systems, IEEE Trans. Parallel Distrib. Syst. (USA), vol. 17 no. 6 (2006), ppt. 508 - 21 , [78] [abs]
    6. Carter, J.R. and Ozev, S. and Sorin, D.J., Circuit-level modeling for concurrent testing of operational defects due to gate oxide breakdown, Proceedings. Design, Automation and Test in Europe, vol. Vol. 1 (2005), ppt. 300 - 5 [abs]
    7. Bower, F.A. and Shealy, P.G. and Ozev, S. and Sorin, D.J., Tolerating hard faults in microprocessor array structures, 2004 International Conference on Dependable Systems and Networks, (2004), ppt. 51 - 60 [abs]
    8. Sorin, D.J. and Martin, M.M.K. and Hill, M.D. and Wood, D.A., SafetyNet: improving the availability of shared memory multiprocessors with global checkpoint/recovery, Proceedings 29th Annual International Symposium on Computer Architecture, (2002), ppt. 123 - 34 , [ISCA.2002.1003568] [abs]

    Awards, Honors, and Distinctions

    • Eta Kappa Nu
    • Intel Graduate Fellowship
    • NSF Early CAREER Award, National Science Foundation
    • Outstanding Graduate Research Award, University of Wisconsin
    • Phi Beta Kappa
    • Tau Beta Pi
    • Top of 2004 - Nanocomputing Research, Technology Research News