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Papers Published

  1. F. A. Bower and D. J. Sorin and L. P. Cox, The impact of dynamically heterogeneous multicore processors on thread scheduling, Ieee Micro, (2008), 17 -- 25, [abs]
  2. A. Meixner and M. E. Bauer and D. J. Sorin, Argus: Low-cost, comprehensive error detection in simple cores, Ieee Micro, (2008), 52 -- 59, [abs]
  3. F. A. Bower and D. J. Sorin and S. Ozev, Online diagnosis of hard faults in microprocessors, Acm Transactions On Architecture And Code Optimization, (2007), [abs]
  4. T. Li and A. R. Lebeck and D. J. Sorin, Spin detection hardware for improved management of multithreaded systems, Ieee Transactions On Parallel And Distributed Systems, (2006), 508 -- 521, [abs]
  5. Bower, F.A. and Sorin, D.J. and Ozev, S., A mechanism for online diagnosis of hard faults in microprocessors, Proceedings. 38th Annual IEEE/ACM International Symposium on Microarchitecture, (2006), 12 pp. -, [abs]
  6. Yilmaz, M. and Hower, D.R. and Ozev, S. and Sorin, D.J., Self-checking and self-diagnosing 32-bit microprocessor multiplier, 2006 IEEE International Test Conference, (2006), 10 pp. -, [abs]
  7. Meixner, A. and Sorin, D.J., Dynamic verification of memory consistency in cache-coherent multithreaded computer architectures, 2006 International Conference on Dependable Systems and Networks, (2006), 10 pp. -, [abs]
  8. Li, T. and Lebeck, A.R. and Sorin, D.J., Spin detection hardware for improved management of multithreaded systems, IEEE Trans. Parallel Distrib. Syst. (USA), (2006), 508 - 21, [78], [abs]
  9. Bower, F.A. and Hower, D. and Yilmaz, M. and Sorin, D.J. and Ozen, S., Applying architectural vulnerability analysis to hard faults in the microprocessor, Perform. Eval. Rev. (USA), (2006), 375 - 6, [abs]
  10. C. Dwyer and A. R. Lebeck and D. J. Sorin, Self-assembled architectures and the temporal aspects of computing, Computer, (2005), 56 -- +, [abs]
  11. Bower, F.A. and Ozev, S. and Sorin, D.J., Autonomic microprocessor execution via self-repairing arrays, IEEE Trans. Dependable Secur. Comput. (USA), (2005), 297 - 310, [44], [abs]
  12. Meixner, A. and Sorin, D.J., Dynamic verification of sequential consistency, Proceedings. 32nd International Symposium on Computer Architecture, (2005), 482 - 93, [abs]
  13. Carter, J.R. and Ozev, S. and Sorin, D.J., Circuit-level modeling for concurrent testing of operational defects due to gate oxide breakdown, Proceedings. Design, Automation and Test in Europe, (2005), 300 - 5, [abs]
  14. Dwyer, C. and Lebeck, A.R. and Sorin, D.J., Self-assembled architectures and the temporal aspects of computing, Computer (USA), (2005), 56 - 64, [34], [abs]
  15. F. A. Bower and S. Ozev and D. J. Sorin, Autonomic microprocessor execution via self-repairing arrays, Ieee Transactions On Dependable And Secure Computing, (2005), 297 -- 310, [abs]
  16. Bower, F.A. and Shealy, P.G. and Ozev, S. and Sorin, D.J., Tolerating hard faults in microprocessor array structures, 2004 International Conference on Dependable Systems and Networks, (2004), 51 - 60, [abs]
  17. Dwyer, C. and Cheung, M. and Sorin, D.J., Semi-empirical SPICE models for carbon nanotube FET logic, 2004 4th IEEE Conference on Nanotechnology (IEEE Cat. No.04TH8757), (2004), 386 - 8, [abs]
  18. Dwyer, C. and Johri, V. and Cheung, M. and Patwardhan, J. and Lebeck, A. and Sorin, D., Design tools for a DNA-guided self-assembling carbon nanotube technology, Nanotechnology, (2004), 1240 - 1245, [022], [abs]
  19. Sorin, D.J. and Martin, M.M.K. and Hill, M.D. and Wood, D.A., Using speculation to simplify multiprocessor design, Proceedings. 18th International Parallel and Distributed Processing Symposium, (2004), 75 -, [IPDPS.2004.1303007], [abs]
  20. Patwardhan, J.P. and Lebeck, A.R. and Sorin, D.J., Communication breakdown: analyzing CPU usage in commercial Web workloads, 2004 IEEE International Symposium on Performance Analysis of Systems and Software (IEEE Cat. No.04EX818), (2004), 12 - 19, [ISPASS.2004.1291351], [abs]
  21. Martin, M.M.K. and Harper, P.J. and Sorin, D.J. and Hill, M.D. and Wood, D.A., Using destination-set prediction to improve the latency/bandwidth tradeoff in shared-memory multiprocessors, Proceedings 30th Annual International Symposium on Computer Architecture, (2003), 206 - 17, [859618.859642], [abs]
  22. Alameldeen, A.R. and Martin, M.M.K. and Mauer, C.J. and Moore, K.E. and Min Xu and Hill, M.D. and Wood, D.A. and Sorin, D.J., Simulating a $2M commercial server on a $2K PC, Computer (USA), (2003), 50 - 7, [MC.2003.1178046], [abs]
  23. Sorin, D.J. and Lemon, J.L. and Eager, D.L. and Vernon, M.K., Analytic evaluation of shared-memory architectures, IEEE Trans. Parallel Distrib. Syst. (USA), (2003), 166 - 80, [TPDS.2003.1178880], [abs]
  24. Sorin, D.J. and Martin, M.M.K. and Hill, M.D. and Wood, D.A., SafetyNet: improving the availability of shared memory multiprocessors with global checkpoint/recovery, Proceedings 29th Annual International Symposium on Computer Architecture, (2002), 123 - 34, [ISCA.2002.1003568], [abs]
  25. Martin, M.M.K. and Sorin, D.J. and Hill, M.D. and Wood, D.A., Bandwidth adaptive snooping, Proceedings Eighth International Symposium on High Performance Computer Architecture, (2002), 251 - 62, [HPCA.2002.995715], [abs]
  26. Sorin, D.J. and Plakal, M. and Condon, A.E. and Hill, M.D. and Martin, M.M.K. and Wood, D.A., Specifying and verifying a broadcast and a multicast snooping cache coherence protocol, IEEE Trans. Parallel Distrib. Syst. (USA), (2002), 556 - 78, [TPDS.2002.1011412], [abs]
  27. Martin, M.M.K. and Sorin, D.J. and Cain, H.W. and Hill, M.D. and Lipasti, M.H., Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing, Proceedings 34th ACM/IEEE International Symposium on Microarchitecture, (2001), 328 - 37, [abs]
  28. Martin, M.M.K. and Sorin, D.J. and Ailamaki, A. and Alameldeen, A.R. and Dickson, R.M. and Mauer, C.J. and Moore, K.E. and Plakal, M. and Hill, M.D. and Wood, D.A., Timestamp snooping: an approach for extending SMPs, Oper. Syst. Rev. (USA), (2000), 25 - 36, [abs]
  29. Eager, D.L. and Sorin, D.J. and Vernon, M.K., AMVA techniques for high service time variability, Performance Evaluation Review, (2000), 217 - 228, [abs]
  30. Martin, M.M.K. and Sorin, D.J. and Ailamaki, A. and Alameldeen, A.R. and Dickson, R.M. and Mauer, C.J. and Moore, K.E. and Plakal, M. and Hill, M.D. and Wood, D.A., Timestamp snooping: An approach for extending SMPs, International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS, (2000), 25 - 36, [378993.378998], [abs]
  31. Condon, A.E. and Hill, M.D. and Plakal, M. and Sorin, D.J., Using Lamport clocks to reason about relaxed memory models, Proceedings Fifth International Symposium on High-Performance Computer Architecture, (1999), 270 - 8, [HPCA.1999.744379], [abs]
  32. Hill, M.D. and Condon, A.E. and Plakal, M. and Sorin, D.J., A system-level specification framework for I/O architectures, SPAA'99. Eleventh Annual ACM Sympsoium on Parallel Algorithms and Architectures, (1999), 138 - 47, [305619.305634], [abs]
  33. Bilir, E.E. and Dickson, R.M. and Ying Hu and Plakal, M. and Sorin, D.J. and Hill, M.D. and Wood, D.A., Multicast snooping: a new coherence method using a multicast address network, Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367), (1999), 294 - 304, [ISCA.1999.765959], [abs]
  34. Plakal, M. and Sorin, D.J. and Condon, A.E. and Hill, M.D., Lamport clocks: verifying a directory cache-coherence protocol, Annual ACM Symposium on Parallel Algorithms and Architectures, (1998), 67 - 76, [277651.277672], [abs]
  35. Sorin, D.J. and Pai, V.S. and Adve, S. and Vemon, M.K. and Wood, D.A., Analytic evaluation of shared-memory systems with ILP processors, Proceedings. 25th Annual International Symposium on Computer Architecture (Cat. No.98CB36235), (1998), 380 - 91, [ISCA.1998.694797], [abs]