Mark Krasniewski

Advisor: Dr. Krishnendu Chakrabarty

1. Background

Today's technology is advancing with increasing rapidity. Scaling of microprocessors is impacting computer chip design enormously. However, as computer circuits become more and more advanced, there are still older pieces of technology that no longer work as stand-alone devices, but are still extremely useful in a newer system. Also, additional specialization in the computer market has given rise to small chips that serve one purpose, and are to be a part of another chip. This trend is integral to a system-on-chip (SOC), which is a computer core consisting of smaller cores that run as part of the larger SOC. As with most computer systems, it is vital that these cores all operate properly, both as individual cores and in conjunction with many other cores. These systems are tested through test access mechanisms (TAMs) and test wrappers. TAMs serve as a gateway for testing equipment to cores, and test wrappers take test patterns from TAMs and deliver them to the cores. This project focused on optimizating test schedules for various SOC configurations.

2. Project Work

While SOC testing has been explored to some degree, it is still an area of diverse scenarios. Two scenarios of interest in this project are hierarchical test access mechanisms and virtual test access mechanisms. Hierarchical TAMs realistically model embedded hierarchies within SOCs. Most experimental work up until now has explored a "flat" hierarchy, meaning all cores are on the same level and there are no restrictions on when a particular core can be scheduled in a test. A hierarchical model requires the use of mega-cores, cores that contain cores within their structure. Sub-cores on a mega-core must only be tested in conjunction with other sub-cores, limiting flexibility in test scheduling. Furthermore, some mega-cores come "pre-packed" from core vendors, meaning that the TAM and test structure of the embedded cores cannot be changed. This limitation provides a further possibility for test scheduling. So two models emerged, interactive and non-interactive hierarchical cores. Algorithms were run to find test schedules for variable width TAMs (interactive case) and fixed width TAMs (non-interactive case).

Virtual TAMs are related to use of high frequency test lines to reduce test time. Newer automatic test equipment (ATE) typically has high frequency test channels, but most current test methods do not call for use of these channels. The implicit cost of purchasing expensive equipment and not using its full capabilities is a relevant issue with a chip manufacturer. Thus, virtual TAMs are presented in this work as a method to use these high frequency channels and at the same time improve testing times. The virtual TAMs are interfaced to the SOC through bandwidth matching, which requires that W_ATE*f_ATE = W_TAM*f_TAM, where f is the frequency of the channel and W is the width. Effectively, high frequency channels on the ATE are used to simulate additional TAM wires on an SOC in testing.

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Results incorporating this work are described in the following jointly authored reports:
V. Iyengar, K. Chakrabarty, M. D. Krasniewski and G. N. Kumar, "Design and optimization of multi-level TAM architectures for hierarchical SOCs", Proc. IEEE VLSI Test Symposium, pp. 299-304, 2003.


A. Sehgal, V. Iyengar, M. D. Krasniewski and K. Chakrabarty, "Test cost reduction for SOCs using virtual TAMs and Lagrange multipliers", accepted for publication in Proc. IEEE/ACM Design Automation Conference, 2003.