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| Lab Objectives | The
objective of this lab exercise is to
introduce the student to sequential circuit design, on paper, in
CAD
tools, with discrete components, and with FPGAs. This lab should
take 1 week (but may be finished at the beginning of lab 7 if
necessary.) You are to design a synchronous modulo-5 up counter two different ways. First, use finite-state machine design techniques (i.e. start with a state diagram, etc.) to design a dedicated mod-5 up counter circuit from scratch. Second, modify a standard mod-8 synchronous counter (prototype designs in your textbook are a good start) to be a mod-5 counter. In both cases, the "events" we will count will be clock pulses (i.e. no separate input switches, and attendant debouncing issues, to deal with). You may use 74LS109 JK FFs or 74LS74 D FFs to implement your designs. In both designs, have your counter trigger a Moore-style output whenever your count reaches "4" (in the sequence 0-1-2-3-4-0-1-2-3-4...). For both designs, begin with a hand design, translate this to a schematic capture design in Quartus II, and simulate your design in Quartus II (the lab TAs will show you how to access a clock signal in your simulations). You will build your two counter designs in two different ways - one will be built with discrete components, and one will be downloaded to the FPGA boards (you can decide which is which). In both cases, use the function generators at each lab station as your clocks, hook one LED to the clock signal (appropriately buffered if necessary), and one LED to your output signal. We should see your output LED blink once for every five blinks of the input LED - slow the function generator down until we can observe this! For whichever counter you implement with discrete components, also hook up the HP logic analyzer to your circuit to observe the input, the output, and the three state variables; verify (and print and record!) the proper state behavior of your design with the logic analyzer. |
| Protocomputer Preparation | 1)
Design (use only structural VHDL and/or LPMs) a 16 bit wide bus
register. The register should have control inputs (INE and OUTE) which
select when the register stores the value on the bus and when the
register asserts its value onto the bus. (in addition to the normal
inputs like Clock.) 2) Instantiate three bus registers and demonstrate data transfer between all pairs. (i.e., A->B, A->C, B->A, B->C, C->A, and C->B). Use the PRN and CLRN present/clear inputs on your registers to initialize them with unique values. |
| Lab Report | Your Lab report should include
the following items: 1) The state diagram, transition tables, excitation tables, and design equations for the brute-force design modulo-5 counter. 2) A description of your mod-8 counter based design. 3) The schematic and waveform traces generated by Quartus for both counters. 4) The printed record from the HP Logic Analyzer used to observe and verify the logical behavior of the counter you built with discrete components. You should arrange to observe the input, output, and all the state variables. 5) Concluding observations and comments 6) Design and results from your bus register simulations |